Some integrated circuits contain field effect transistors (FETs) with drift regions to enable higher voltage operation. As these integrated circuits are scaled to the next generation of products, there is a desire to increase the switching frequency of these FETs to reduce the sizes of the external passive components such as inductors while maintaining a low power dissipation in these FETs. This requires simultaneously reducing the switching parasitics and the on-state specific resistances (the area-normalized on-state resistances) of the FETs.
To enable operation at elevated drain voltage, the FETs employ drift regions that deplete under high drain voltage conditions, allowing the FETs to block the voltage while supporting conduction during the on-state. A higher voltage FET tends to be formed with the gate extending over field oxide in order to act as a field plate for the drift region. Unfortunately, field oxide in advanced fabrication nodes such as the 250 nanometer node and beyond is commonly formed by shallow trench isolation (STI) processes, and is generally too thick for optimal use as a field relief oxide under a gate extension field plate in such a FET.